As large-scale integration continues to drive the microelectronic industry toward lower costs, the requirements for deposition and etching techniques leading to smaller geometries with improved process controls become more and more stringent. In this regard, it is now widely accepted that Atomic Layer Processing of materials is a key-enabling technology for the fabrication of nanoscale devices.
Atomic Layer Deposition (ALD) has gradually become an invaluable technique from 2007 when it was sucessfully implemented by Intel for the mass production of HfO2 gate oxide-based CMOS at the 45 nm technological node. From then on, it has been keeping on spreading at a steady pace in both Front- and Back-End of Line processes, thanks to its unequalled benefits : improved thin film growth characteristics with atomic scale thickness control, in situ doping at atomic level for improved materials properties, excellent step coverage and large area uniformity. In plasma equipped ALD tools (PE-ALD), deposition temperature can also be significantly lowered, opening the way to device processing at reduced thermal budgets and on flexible substrates. The use of plasma sources is particularly relevant for Atomic Layer Etching (ALE) applications whose development is also driven by ALD.
Thus, with the most recent developments in ALD and ALE, the logic and memory semiconductor industry is gradually migrating from lithography enabled 2D devices to 3D architectures and devices (e.g. FinFET) with sub-10 nm size. This inflection has boosted demands for new patterning films, new conformal materials, and mostly new bottom-up approaches such as Area Selective Deposition (ASD).
In this presentation, a few state of the art technological processes based on PEALD combined with ALE will be presented. Fabrication of nanoscale devices and process control with acceptable feature size variability down to 3 or 4 silicon atoms will be discussed, in view of the capabilities offered by global Atomic Layer Processing of materials.